As AI workloads grow, networking has become the primary governor of performance, where congestion or stalled packets directly impact revenue and efficiency. Arista Networks emphasizes three foundational design strategies for AI infrastructure: scale-up, scale-out, and scale-across. Scale-up focuses on intra-rack interconnectivity, using high-speed switches to allow multiple accelerators (XPUs) to access a shared memory pool for improved computational density. Liquid cooling and low-power interconnects like co-packaged copper or optics (CPC/CPO) are essential for managing heat and power in these high-density racks.

Scale-out involves horizontal growth across multiple servers or nodes to handle parallelized training and inference. By utilizing a flat, two-tier leaf-spine network topology with massive radix, operators can maximize XPU connectivity while maintaining bisection bandwidth without the power penalties of additional tiers. Scale-across extends this capability across multiple geographical locations, pooling physically separated AI clusters for frontier-scale jobs. This requires complex routing features and hierarchical deep buffers to manage the transient congestion and micro-bursts that occur in distributed environments.

Arista is introducing unified AI fabrics that integrate these three scales into a cohesive system. The Arista Etherlink platforms optimize performance through the Multipath Reliable Connection (MRC) protocol, which uses hardware-accelerated packet trimming and intelligent buffering to reduce tail latency. The 7800 AI Spine provides a high-radix spine layer that enables metro mesh topologies, allowing inter-cluster traffic to be offloaded and routed seamlessly. These systems are managed through Arista’s EOS, which supports SRv6 micro-segment identifiers (uSID) to enable fine-grained, source-routed steering of AI traffic.

The transition to these intelligent fabrics allows AI centers to move away from rigid, static 3-tier legacy networks toward adaptive, multi-planar designs. As AI models shift from strictly east-west traffic to synchronized, all-to-all collective communication, these networks must handle both massive training bursts and concurrent real-time inference swarms. The current evolution supports lane speeds from 112G SerDes to 224G, with 448G per lane on the horizon. By converging hardware and software networking, these fabrics aim to provide consistent, resilient architectures that can scale from thousands to millions of AI accelerators while maintaining the economic simplicity of a two-tier design.

As AI workloads grow, networking has become the primary governor of performance, where congestion or stalled packets directly impact revenue and efficiency. Arista Networks emphasizes three foundational design strategies for AI infrastructure: scale-up, scale-out, and scale-across. Scale-up focuses on intra-rack interconnectivity, using high-speed switches to allow multiple accelerators (XPUs) to access a shared memory pool for improved computational density. Liquid cooling and low-power interconnects like co-packaged copper or optics (CPC/CPO) are essential for managing heat and power in these high-density racks.

Scale-out involves horizontal growth across multiple servers or nodes to handle parallelized training and inference. By utilizing a flat, two-tier leaf-spine network topology with massive radix, operators can maximize XPU connectivity while maintaining bisection bandwidth without the power penalties of additional tiers. Scale-across extends this capability across multiple geographical locations, pooling physically separated AI clusters for frontier-scale jobs. This requires complex routing features and hierarchical deep buffers to manage the transient congestion and micro-bursts that occur in distributed environments.

Arista is introducing unified AI fabrics that integrate these three scales into a cohesive system. The Arista Etherlink platforms optimize performance through the Multipath Reliable Connection (MRC) protocol, which uses hardware-accelerated packet trimming and intelligent buffering to reduce tail latency. The 7800 AI Spine provides a high-radix spine layer that enables metro mesh topologies, allowing inter-cluster traffic to be offloaded and routed seamlessly. These systems are managed through Arista’s EOS, which supports SRv6 micro-segment identifiers (uSID) to enable fine-grained, source-routed steering of AI traffic.

The transition to these intelligent fabrics allows AI centers to move away from rigid, static 3-tier legacy networks toward adaptive, multi-planar designs. As AI models shift from strictly east-west traffic to synchronized, all-to-all collective communication, these networks must handle both massive training bursts and concurrent real-time inference swarms. The current evolution supports lane speeds from 112G SerDes to 224G, with 448G per lane on the horizon. By converging hardware and software networking, these fabrics aim to provide consistent, resilient architectures that can scale from thousands to millions of AI accelerators while maintaining the economic simplicity of a two-tier design.