Halley Predicts Failures in Optical AI Networks

HuggingFaceFriday, November 6, 2026
Halley Predicts Failures in Optical AI Networks
  • •Halley framework forecasts failures and controls resources across optical AI data center networks
  • •Simulation goodput rose from 65.2% to 76.5%, or 67.4% when only affected channels lost bandwidth
  • •Paper reports up to 1.03–1.17 times training per megawatt and 3.3–14.7% less capacity needed

Researchers Manav Mishra and Krishna M. Sivalingam published Halley, a predictive control framework for optical networks in AI data centers, on November 3. The framework forecasts equipment failures and adjusts network resources in advance, with formal guarantees for its components. The paper says the approach improves effective throughput while reducing the capacity needed for a given amount of training.

AI training clusters connect tens of thousands of accelerators through dedicated networks, and the devices exchange data at every training step. Optical links between racks have four layers, from lasers to switches, which the paper says typically use fixed or after-the-fact policies. Lasers in the same enclosure can share cooling and power, allowing failures to occur together; at a fixed spare ratio, such correlated failures cap the availability of a laser pool regardless of its size.

Halley has four components: LightReserve sizes the laser pool to meet a coverage bound; FoldFit schedules switches within 11/9 of the optimal; ThermaLead controls microring devices one step ahead; and TriageGuard protects the modules at highest risk first. Each layer defers to the deployed policy when its prediction is uncertain. In simulations, effective goodput—the share of ideal throughput retained—rose from 65.2% to 76.5% when exhausting spare capacity meant losing an entire window, and reached 67.4% when only dark channels lost bandwidth. The paper reports up to 1.03–1.17 times as much training per megawatt, or 3.3–14.7% less data center capacity for the same training. Halley’s fallback circuits were formally verified, achieved close timing on a commercial FPGA, and passed a 130 nm signoff.