Qualcomm Validates HBC for AI250 Accelerator

Qualcomm has completed initial hardware validation of its first-generation High Bandwidth Compute (HBC) technology, a step toward commercialization, and plans to debut it in the Dragonfly AI250 accelerator, which is scheduled to begin sampling in the first half of 2027. ServeTheHome reported that Qualcomm tested HBC’s memory read-write and near-memory computing capabilities. The company first unveiled HBC earlier this year.

HBC stacks LPDDR memory directly on a compute die, processing data closer to where it is stored. Unlike conventional HBM, which connects memory stacks to a separate processor, HBC is designed to reduce data movement and power consumption while potentially lowering manufacturing costs. Qualcomm measured more than 5× HBM4’s bandwidth-per-watt efficiency, based on HBM4 specifications, and reported 18 times the bandwidth of external LPDDR5X; it has not disclosed specific bandwidth figures.

ServeTheHome says HBC could also reduce packaging cost and complexity. Conventional HBM uses advanced packaging such as CoWoS or EMIB to connect memory stacks, compute dies and controllers through an ultra-wide interface. HBC moves more computation to the die beneath the memory stack, reducing the bandwidth needed to communicate with the main processor and potentially allowing less expensive conventional 2D organic substrates. It uses LPDDR5X DRAM dies instead of specialized HBM DRAM dies, which may reduce costs. Qualcomm has not disclosed final performance specifications, but HBC stacks are expected to offer greater memory capacity than current HBM4 implementations.

The Elec previously reported that Samsung Electronics and SK hynix were working with Qualcomm on HBC commercialization, with TSMC expected to support technology integration and advanced packaging; the companies have not publicly confirmed specific production arrangements. Qualcomm said in June that its next-generation Dragonfly AI300 will use second-generation HBC, targeting 54 times the effective memory bandwidth of the LPDDR5X-based AI200, with sampling expected in 2028.

Qualcomm has completed initial hardware validation of its first-generation High Bandwidth Compute (HBC) technology, a step toward commercialization, and plans to debut it in the Dragonfly AI250 accelerator, which is scheduled to begin sampling in the first half of 2027. ServeTheHome reported that Qualcomm tested HBC’s memory read-write and near-memory computing capabilities. The company first unveiled HBC earlier this year.

HBC stacks LPDDR memory directly on a compute die, processing data closer to where it is stored. Unlike conventional HBM, which connects memory stacks to a separate processor, HBC is designed to reduce data movement and power consumption while potentially lowering manufacturing costs. Qualcomm measured more than 5× HBM4’s bandwidth-per-watt efficiency, based on HBM4 specifications, and reported 18 times the bandwidth of external LPDDR5X; it has not disclosed specific bandwidth figures.

ServeTheHome says HBC could also reduce packaging cost and complexity. Conventional HBM uses advanced packaging such as CoWoS or EMIB to connect memory stacks, compute dies and controllers through an ultra-wide interface. HBC moves more computation to the die beneath the memory stack, reducing the bandwidth needed to communicate with the main processor and potentially allowing less expensive conventional 2D organic substrates. It uses LPDDR5X DRAM dies instead of specialized HBM DRAM dies, which may reduce costs. Qualcomm has not disclosed final performance specifications, but HBC stacks are expected to offer greater memory capacity than current HBM4 implementations.

The Elec previously reported that Samsung Electronics and SK hynix were working with Qualcomm on HBC commercialization, with TSMC expected to support technology integration and advanced packaging; the companies have not publicly confirmed specific production arrangements. Qualcomm said in June that its next-generation Dragonfly AI300 will use second-generation HBC, targeting 54 times the effective memory bandwidth of the LPDDR5X-based AI200, with sampling expected in 2028.