Samsung Electronics is preparing heat-management technologies for HBM4E as AI packages grow larger, with mass production planned to begin next year. Reports cited by TrendForce say interposers connecting compute chips and high-bandwidth memory (HBM) are expanding, making heat dissipation a greater challenge.

Current AI interposers are about 5.5 times the 858 mm² maximum area an EUV lithography system can expose in one shot. A semiconductor equipment industry official expects HBM interposers to grow to nine times, 12 times and eventually up to 40 times that area. The growth reflects process-scaling limits and wider use of chiplet-based 2.5D packaging, which combines multiple compute chiplets and HBM stacks on one interposer as a single advanced chip cannot meet AI workloads’ computing requirements.

Samsung is considering hybrid copper bonding (HCB), which replaces microscopic bumps between stacked DRAM dies with direct copper-to-copper connections. Smaller gaps can make the stack thinner and improve heat dissipation. Samsung showed HCB at NVIDIA’s GTC 2026 in March. Its other option, a heat path block (HPB), is designed to reduce heat without hybrid bonding.

At COMPUTEX 2026, Samsung identified the D2D PHY in HBM’s base die—the interface for high-speed data transfers between HBM and a GPU—as a major heat source. HPB creates a dedicated thermal path around it to dissipate heat and reduce thermal resistance. Samsung is validating HPB with HBM4E and plans to introduce it with HBM5. SK hynix’s iHBM places highly thermally conductive but electrically insulating cooling material around the D2D PHY; the company expects it to reduce thermal resistance by around 30%.

Samsung Electronics is preparing heat-management technologies for HBM4E as AI packages grow larger, with mass production planned to begin next year. Reports cited by TrendForce say interposers connecting compute chips and high-bandwidth memory (HBM) are expanding, making heat dissipation a greater challenge.

Current AI interposers are about 5.5 times the 858 mm² maximum area an EUV lithography system can expose in one shot. A semiconductor equipment industry official expects HBM interposers to grow to nine times, 12 times and eventually up to 40 times that area. The growth reflects process-scaling limits and wider use of chiplet-based 2.5D packaging, which combines multiple compute chiplets and HBM stacks on one interposer as a single advanced chip cannot meet AI workloads’ computing requirements.

Samsung is considering hybrid copper bonding (HCB), which replaces microscopic bumps between stacked DRAM dies with direct copper-to-copper connections. Smaller gaps can make the stack thinner and improve heat dissipation. Samsung showed HCB at NVIDIA’s GTC 2026 in March. Its other option, a heat path block (HPB), is designed to reduce heat without hybrid bonding.

At COMPUTEX 2026, Samsung identified the D2D PHY in HBM’s base die—the interface for high-speed data transfers between HBM and a GPU—as a major heat source. HPB creates a dedicated thermal path around it to dissipate heat and reduce thermal resistance. Samsung is validating HPB with HBM4E and plans to introduce it with HBM5. SK hynix’s iHBM places highly thermally conductive but electrically insulating cooling material around the D2D PHY; the company expects it to reduce thermal resistance by around 30%.