Tohoku University and Aisin Develop STT-MRAM AI Chip

Tohoku University and Aisin announced on November 2, 2026, that they had developed an AI chip with built-in STT-MRAM, without external DRAM or SSD. The chip uses near-memory computing, which processes data close to where it is stored. The companies said it starts the operating system about 39 times faster, reduces processing time for tasks such as object detection to about one-tenth, and cuts energy use for AI processing to one-fiftieth of the conventional level.

The project was led by teams from Tohoku University’s Center for Innovative Integrated Electronic Systems, headed by Professor Tetsuo Endo, and Aisin. Manufactured using TSMC’s 16-nanometer FinFET process, the chip integrates 32 MB of STT-MRAM, an AI accelerator, a two-core Arm Cortex-A53 CPU, and a Mali-G31 GPU. The news release describes it as the world’s first 16-nanometer AI system-on-chip with STT-MRAM.

The STT-MRAM stores AI model weights and operating system boot data. In the conventional setup, DRAM is initialized after power-on, then data for the U-Boot bootloader and AI model is transferred from an SSD to DRAM. The new chip keeps the required startup data and model weights in STT-MRAM, reducing DRAM initialization and transfers from external memory. The companies said the time from power-on to OS kernel startup fell from 2,535.3 milliseconds (about 2.5 seconds) to 65.7 milliseconds, a 38.59-fold speedup.

To run the Tiny YOLOv3 image-recognition model on the AI accelerator while making use of limited STT-MRAM, the teams developed a hybrid multiplication architecture combining 8-bit and 16-bit operations. It combines 16×16-bit, 16×8-bit, and 8×8-bit multiplication, retaining 16-bit precision while compressing weight data from 17.7 MB to 9.36 MB, a 53% reduction. The reported mean average precision (mAP), a measure of object-detection accuracy, declined from 0.325 to 0.316. A weight-sharing technique also reuses weights for the same kernel across multiple clock cycles within 4×4 tiles, reducing data movement and local bandwidth use.

The conventional system transferred 12 MB of weight data from SSD to DRAM before processing; the new chip reads the needed weights directly from STT-MRAM. The teams measured a reduction in standalone chip AI processing time from 594.6 milliseconds to 58.5 milliseconds and about a 25-fold speedup at the system level. They said Tiny YOLOv3 inference used 50.7 millijoules per frame, about one-fiftieth the conventional energy. The research is scheduled to be presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, held in Hsinchu, Taiwan, from November 1 to 4, 2026.

Tohoku University and Aisin announced on November 2, 2026, that they had developed an AI chip with built-in STT-MRAM, without external DRAM or SSD. The chip uses near-memory computing, which processes data close to where it is stored. The companies said it starts the operating system about 39 times faster, reduces processing time for tasks such as object detection to about one-tenth, and cuts energy use for AI processing to one-fiftieth of the conventional level.

The project was led by teams from Tohoku University’s Center for Innovative Integrated Electronic Systems, headed by Professor Tetsuo Endo, and Aisin. Manufactured using TSMC’s 16-nanometer FinFET process, the chip integrates 32 MB of STT-MRAM, an AI accelerator, a two-core Arm Cortex-A53 CPU, and a Mali-G31 GPU. The news release describes it as the world’s first 16-nanometer AI system-on-chip with STT-MRAM.

The STT-MRAM stores AI model weights and operating system boot data. In the conventional setup, DRAM is initialized after power-on, then data for the U-Boot bootloader and AI model is transferred from an SSD to DRAM. The new chip keeps the required startup data and model weights in STT-MRAM, reducing DRAM initialization and transfers from external memory. The companies said the time from power-on to OS kernel startup fell from 2,535.3 milliseconds (about 2.5 seconds) to 65.7 milliseconds, a 38.59-fold speedup.

To run the Tiny YOLOv3 image-recognition model on the AI accelerator while making use of limited STT-MRAM, the teams developed a hybrid multiplication architecture combining 8-bit and 16-bit operations. It combines 16×16-bit, 16×8-bit, and 8×8-bit multiplication, retaining 16-bit precision while compressing weight data from 17.7 MB to 9.36 MB, a 53% reduction. The reported mean average precision (mAP), a measure of object-detection accuracy, declined from 0.325 to 0.316. A weight-sharing technique also reuses weights for the same kernel across multiple clock cycles within 4×4 tiles, reducing data movement and local bandwidth use.

The conventional system transferred 12 MB of weight data from SSD to DRAM before processing; the new chip reads the needed weights directly from STT-MRAM. The teams measured a reduction in standalone chip AI processing time from 594.6 milliseconds to 58.5 milliseconds and about a 25-fold speedup at the system level. They said Tiny YOLOv3 inference used 50.7 millijoules per frame, about one-fiftieth the conventional energy. The research is scheduled to be presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, held in Hsinchu, Taiwan, from November 1 to 4, 2026.